Support Single Port MIPI CSI/DSI Input, Compliant with D-PHY 1.2,DSU 1.3 and CSI 1.3, Clock lane and 1~4 configurable data lanes, 80Mb/s~2.0Gb/s per data lane, Support 16/18/24/30/36-bit RGB and YUV format, Support Burst and Non-Burst Mode
“Reaching High-Speed and High-Resolution Architecture: IMX925/935 and the Power of SLVS-EC”
May 12th, 10.00 – 10.45AM CEST
